1. Field of the Invention
The present invention relates generally to the field of analog signal processing integrated circuits, and more specifically, to operational amplifiers.
2. Background Information
One of the basic building blocks for analog signal processing integrated circuits is the operational amplifier. It is used in various applications such as, for example, voltage buffering circuits, gain/attenuator circuits, switched capacitor circuits, voltage references, active filters, etc. The basic parameters and/or specifications to consider for operational amplifiers include the open loop gain, gain bandwidth product, output voltage swing, input common mode range, offset voltage, and power consumption. The most basic configuration of an operational amplifier is a two stage architecture, which is simple to stabilize and provides high gain. Namely, the two stage architecture consists of an input differential stage and an output stage. The input differential stage is used to provide an offset and common mode rejection while the output stage is used to provide a high gain.
At a low voltage power supply (e.g., 3 volts), the output voltage swing is severely limited. In the present invention, by using a voltage multiplier to supply only the output stage, the voltage multiplier is more power efficient and the output voltage swing is much higher than the available power supply voltage. This is extremely advantageous in applications where a high voltage swing is only needed at the output and not at the input such as, for example, in gain configurations and switched capacitor gain circuits. In addition, to operate at a high voltage (e.g., 20 volts), the conventional approach uses high voltage transistors (i.e., a high voltage process is needed). The present invention, however, utilizes only regular low voltage NMOS and PMOS devices as used in regular digital/analog low voltage circuits without such devices suffering from any breakdown problems. High voltage operation of an operational amplifier requires careful consideration of latchup conditions, noise couplings, and breakdown of devices. The present invention provides techniques to prevent such latchup conditions, noise couplings, and breakdown of devices.
In prior art U.S. Pat. No. 5,631,606 issued to Tran, the input stage and the intermediate stages have their power supplied from a voltage multiplier which allows the gates of the output MOS transistor to be much higher, resulting in a smaller size MOS transistor. But the output voltage itself is limited by the regular power supply. In the present invention, on the other hand, the output stage is powered by a high voltage multiplier which allows the output voltage to swing much higher than the voltage swing of the regular power supply. Moreover, in the '606 patent, the operational amplifier cannot operate at a high voltage (e.g., 20 V) because breakdown conditions of MOS transistors would be violated. In contrast, the operational amplifier of the present invention operates at a high voltage without violating any breakdown conditions.